In the manufacture of devices requiring high degree of miniaturization and integration, such as NAND-type flash memories, there exists a method where a number of semiconductor chips having a thin-cross-section are stacked together and interconnected front to back and then sealed with a resin, i.e., laminated and then sealed in resin. Another method exists where semiconductor chips are sealed with a resin and then a number of layers of the resin-sealed semiconductor chips are interconnected. Wire-bonding is generally used for providing communication of signals from the respective semiconductor chips. However, to increase the signal transmission speed, a laminating system using TSV (through silicon VIA) is currently proposed. An example of this laminating system includes sequentially laminating chips one over the other on a carrier substrate made of metal and the carrier substrate is provided with a member for preventing outflow of sealing material therefrom. The spaces between the chips are sealed with resin in a manner where bumps of interface chips on the uppermost layer can be exposed. Then, discrete wiring substrates are joined to connection terminals of the interface chips on the uppermost layer. After the peripheral portions of the chips are sealed by molding, the carrier substrate with the molded resin thereabout is diced. While this method is a highly efficient mounting method, the necessity of enlarging the carrier substrate in accordance with the volume of the member for preventing outflow of sealing material increases the package size. In addition, the finish of the surface produced by dicing using a blade is less than satisfactory.